Processor provisioning by a middleware processing system

ABSTRACT

A middleware processor provisioning process provisions a plurality of processors in a multi-processor environment. The processors themselves may be subdivided in to one or more partitions or processing instances for which a single processing queue is created and a single kernel thread is started. User processing requests are portioned and dispatched across the plurality of processing queues and are serviced by the corresponding kernel process, thereby efficiently using available processing resources while servicing the user processing requests in a desired manner.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/723,569, entitled “PROCESSOR PROVISIONING BY A MIDDLEWARE PROCESSINGSYSTEM” and filed Dec. 21, 2012, the disclosure of which is incorporatedherein by reference in its entirety.

BACKGROUND

1. Technical Field

Present invention embodiments relate to processor provisioning, and morespecifically, to processor provisioning by way of a middlewareprocessing system.

2. Discussion of the Related Art

Central Processing Unit (CPU) or processor provisioning is a commonactivity performed in modern computer systems to manage processingworkload, e.g., in personal computing devices such PCs or tablets, bladeservers, or mainframe type computers. In these applications, availableprocessing capacity is allocated among a plurality of user or systemapplications and processes. For example, in a real-time operating system(RTOS) available processing power is allocated in units of time, such astime slices, as well as by a process priority. Furthermore, memory maybe partitioned on a per process basis. Processing and memory allocationmay be controlled via control tokens or mutually exclusive (mutex)control for concurrent computing processes and memory allocation.

Traditional approaches to workload management have also beenincorporated into middleware software systems (MSSs). Workloadmanagement capabilities are a key feature for middleware softwaresystems that support mixed workload or multi-tenancy environments (e.g.,database servers). Such systems may need to simultaneously supportdiverse applications from different areas in the enterprise withdiffering resource and service level requirements. As such, it isimportant to have the capability to be able to prioritize the executionof different applications in order to facilitate effective resourcesharing and to ensure that their processing resources are adequatelyinsulated from each other and able to meet their service levelperformance goals.

Although there are a multitude of workload management techniques thatcan indirectly affect the division of resources between workloads(including managing the number of concurrently executing requests and/ormechanisms that alter the priority of threads or processes executingdifferent tasks), the capabilities that have been observed to providethe most predictable level of control and insulation are those thatallow the user to exert direct control over the amount of CPU given tothe different workloads running on the system. However, such systems donot adequately scale in middleware environments, for example, due toscheduling conflicts that arise as the number of processes beingserviced increases.

BRIEF SUMMARY

According to one embodiment of the present invention, a methodimplemented by a computer via a middleware processing system efficientlyallocates workload for a plurality of user processing requests ofdiffering priority among a plurality of processors or processor cores ina multiprocessor system. A current processing workload is assessed forthe plurality of user processing requests. The processing capability ofthe multiprocessor system is subdivided into a plurality of processingunits (e.g., based on the current processing workload). One or moreprotected processes (e.g., a kernel process) are started to service theuser processing requests and a processing queue is generated for each ofthe processing units. A portion of each user processing request isassigned to one or more of the processing queues; and serviced by theone or more protected processes.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a diagrammatic illustration of an example computingenvironment for use with an embodiment of the present invention.

FIG. 2 is a process flow diagram illustrating a manner in which userrequests are processed according to an embodiment of the presentinvention.

FIGS. 3A and 3B are diagrammatic illustrations of operation of runtimedispatching queues according to an embodiment of the present invention.

FIG. 4 is a diagrammatic illustration of operation of runtimedispatching queues when service classes are employed according to anembodiment of the present invention.

FIG. 5 is a flow diagram illustrating a manner in which CPU processingis allocated in a multiprocessor environment according to an embodimentof the present invention.

FIG. 6 is a procedural flow chart of operation of runtime dispatchingqueues in a multi-partitioned multiprocessor environment according to anembodiment of the present invention.

DETAILED DESCRIPTION

Present invention embodiments optimize workload processing across aplurality of processors in a multiprocessor environment (e.g., in aserver farm). Embodiments described herein use a one to one (1:1)threading model that maps user processes onto processing queues witheach processing queue having access to a service process that serviceseach user process (i.e., one user process to one service process) as itcomes off a queue. The queues thus map user processes to operatingsystems (OS) processes that run under protected execution (e.g., in akernel space).

For example, if three user processes are contending for resources on twoprocessors, four queues may be set up for the two processors. A singleprocess for each queue is started for each queue across the twoprocessors. Any combination may be set up that efficiently process thethree user processing requests. For example, three kernel processes maybe set on one processor and a single kernel process on the otherprocessor, or two kernel processes may be set up on each processor. Theuser processing is then time sliced across the four queues in a mannerthat provides that best or most efficient processing of the userprocessing requests. If a user request does not finish during its queuetime slice allotment then the user processing request is recycled backonto one of the queues. Further details of this queuing arrangement aredescribed below.

Common workload management techniques include CPU shares, soft limits,and hard limits. CPU shares allow the user to define the target CPUallocation for a workload in terms of a numeric share value thatrepresents the relative proportion of CPU the workload should receivecompared to other workloads on the system. IBM's AIX operating systemand Linux' workload manager (WLM) both support the concept of shares. Asan example, if Workload A is assigned 400 shares, Workload B is assigned400 shares, and Workload C is assigned 200 shares for a total allocationof 1000 shares. The relative allocation of CPU between the threeworkloads would be 40% (400/1000) for Workload A, 40% (400/1000) forWorkload ft and 20% (200/1000) for Workload C. If Workload C finishesand only Workload A and B are left running the target allocation wouldbe 50% CPU for each workload, since each represents 400 shares out of atotal of 800 shares.

Thus, when the workloads running on the system are competing for CPUtime the workload manager ensures that the CPU is assigned based on theshares based target allocation. When the system is not fully utilizedand workloads are not competing for CPU, workloads are allowed toconsume the idle processing capacity as needed.

The shares concept generally offers the most appealing and flexiblemodel for managing the CPU assigned to different workloads as the sharebased allocations are relative to which other workloads are running onthe system, meaning that the allocations grow or shrink accordinglydepending on how many active workloads are running. Allowing workloadsaccess to idle CPU capacity in the absence of competition for the CPUalso ensures efficient use of machine resources.

Soft limits behave in a similar manner to CPU shares, except that theCPU allocations for workloads are specified as a fixed percentage of themachine resources, rather than as a relative share. AIX WLM supportssoft limits in addition to CPU shares, while Linux WLM does not. Withsoft limits, idle CPU time may be accessed since it is allocated a“soft” percentage of CPU time. For example, when Workload C dropsoffline as in the example above, Workload A and Workload B can stillcommand 50% of the available CPU time by sharing Workload C's 20% CPUallocation.

Hard limits provide the capability for the user to specify a strict CPUconsumption limit for a workload specified as a percentage of theoverall CPU capacity available on the host machine.

Although such workload management capabilities are implemented andavailable through some operating system workload managers like AIX andLinux WLM, it is advantageous to be able to implement this type ofcapability directly into the middleware software for several reasons:

-   -   By implementing the capabilities in the middleware, consistent        support can be provided across all the platforms the middleware        supports. For a cross-platform product, workload management        solutions that rely on OS facilities differ in terms of        capabilities on each platform, and may not be available at all        on some platforms. For example, the OS WLM integration available        in DB2 for LUW enables CPU shares, soft limit, and hard limit        based controls on AIX, CPU shares only on Linux, and has no        support on platforms such as Solaris, HP and Windows.    -   Having the support directly in the middleware also means that        the capabilities can generally be configured through        administrative functions on the middleware product itself. This        can be important in cases where the people and processes that        configure the underlying hardware and OS are different from        those administering the software (e.g., database administrators        vs. system administrators). For distributed middleware solutions        this also generally means that the configuration can be        administered through a single point of control, rather than        needing to be setup individually on each host in a distributed        cluster.    -   Workload management capabilities that are integrated into the        middleware can leverage internal state information that would        not otherwise be available to make more optimal scheduling        decisions (e.g., to avoid priority inversion issues when        multiple tasks of different priorities are competing for        exclusive access on the same object).

In order to provide middleware based workload control that issufficiently fine grained to accurately provision CPU usage betweenjobs, it is generally necessary to implement some form of cooperativetask scheduling or time slicing in the software. Under this type ofmodel, jobs are given a short duration of time on the processors andthen required to return to a run queue where the software prioritizewhen the task is dispatched next relative to other jobs waiting to runon the system. Unfortunately, there are significant challenges inimplementing such a mechanism, especially in cases where it is beingintroduced as a new feature on an existing software system.

The typical way to implement such a solution would be by using an M:Nthreading model where M user threads are managed by the software andscheduled amongst N kernel worker threads with N based on the number oftasks allowed to be dispatched to the actual system CPUs at a time(typically equivalent to the number of CPUs on the system). This modelallows the software to effectively manage its own CPU run queues,dispatching only the number of tasks that can be run in parallel at atime by the OS, and provisioning access to the CPU by the priority orderin which tasks are dispatched. Historically a user threading model wasalso beneficial due to the possibility of reducing context switchingcosts between threads, but with a steady increase in processor speeds,this benefit by and large has been amortized away. On the flip sidehowever, this type of threading model can have significant drawbacks,especially when the goal is to add workload management capabilities toan existing system that is based on a 1:1 thread based or process basedmodel. Specifically:

-   -   An M:N model necessitates that worker threads offload blocking        activities like network communications and I/O to other threads,        and this can introduce additional latencies in the processing        that degrade performance when compared to a 1:1 threading model.    -   Synchronization primitives relying on OS level calls, or        implemented as spin locks, need to be rewritten to support        queuing of waiting worker threads, and this can have negative        performance implications in cases where the synchronization        primitives have been highly optimized for the product.    -   The general costs of re-architecting an existing system to        change to an M:N threading model can be prohibitive as many        existing subsystems may need to be redesigned from scratch (in        addition to the I/O subsystem and synchronization primitives,        other mechanisms such as those that rely on signals to drive        notifications or asynchronous processing not operate in a        user-threaded architecture and would need to be redesigned).

In addition to challenges related specifically to the threading model,there are a number of other challenges that need to be surmounted whenimplementing granular task management in middleware software:

-   -   A middleware solution is forced to rely on cooperative task        scheduling (due to the inability to preempt tasks like the OS),        and cooperative task scheduling by nature lacks any concept of a        predefined preemptive time slice. A task typically yields back        to the scheduler when it is required to block on some type of        synchronization primitive, I/O, or at some well known yield        point in processing. This means that the length of a time slice        in such a system varies widely; making it difficult to normalize        dispatching in order to ensure the task achieves its desired CPU        provisioning. This is an especially important problem when the        intention is to support specific CPU limits being imposed on        applications.    -   A second related issue is that a processor intensive task that        does not perform any blocking operations in this type of system,        needs to explicitly yield to return control to the scheduler;        making it very difficult to strike a balance where control can        be yielded on a reasonably frequent basis to allow effective        control, but not so frequently as to affect the task        performance, since it is difficult to judge how to space out the        yield calls in the code. This is another factor that can make it        difficult to enforce accurate CPU utilization limits where the        desire is to provide strict resource isolation for specific        workloads.    -   Scheduling to achieve specific CPU provisioning in middleware        requires the tracking of the CPU usage of individual threads        running on behalf of particular workloads in the software. The        cost of querying the CPU time used for a thread executing a task        from the OS is relatively expensive and degrades performance if        queried too frequently. A task scheduler by definition may be        required execute granular time slices for tasks that perform a        lot of blocking operations (consider that in a transactional        database system, individual requests may execute in a range as        small as tens of microseconds between communication with the        client), which means that a middleware based solution often        needs to incur undesired overhead to be able to provide the        desired provisioning capabilities.    -   Environments with virtualization, which are becoming        increasingly common, increase the difficulty of supporting        specific CPU utilization limits on certain jobs, as the CPU        utilization calculations vary depending on the CPU capacity        allocated to the host by the hypervisor rather than simply the        number of cores on the host. Typical middleware systems that do        not account for virtualization are unable to enforce correct CPU        limits in virtualized environments, as they are calculating the        limits based on the assumption of dedicated CPUs rather than        micro-partitioned CPUs    -   Having the middleware manage an additional run queues on top of        the OS can introduce scalability problems in the case where a        single run queue is used (which represents a global        serialization point/bottleneck), or difficulties in performing        accurate scheduling if the scheduling is split up and managed        separately across independent run queues.

In the context of these technical challenges a typical middlewaresolution chooses to either scale back the overall functionality andaccuracy of CPU provisioning offered (for example, by offering a lessaccurate level of CPU control in order to reduce overhead, and/oreschewing the ability to enforce specific CPU limits in favor ofproviding only relative prioritization), or instead opt to use OS levelfacilities that can bypass the challenges of implementing the CPUprovisioning within the middleware but also at a cost of the potentialbenefits mentioned earlier.

A technique for implementing a low overhead scalable CPU provisioningmechanism in a middleware software system is introduced herein. Thistechnique can provide capabilities similar to those capabilitiesavailable to an OS WLM without requiring a large scale re architectureto integrate into an existing system. The technique provides thecapability for implementing both accurate CPU shares and CPU limitcontrols within the middleware platform with low overhead, carrying allthe associated benefits of an integrated cross-platform solutiondescribed above. The technique uses several novel techniques to overcomeobstacles that would normally impede the implementations of such asystem without making the tradeoffs discussed above.

An example environment for use with present invention embodiments isillustrated in FIG. 1. Specifically, the environment includes one ormore server systems 10, and one or more client or end-user systems 14.Server systems 10 and client systems 14 may be remote from each otherand communicate over a network 12. The network may be implemented by anynumber of any suitable communications media (e.g., wide area network(WAN), local area network (LAN), Internet, intranet, etc.).Alternatively, server systems 10 and client systems 14 may be local toeach other, and communicate via any appropriate local communicationmedium (e.g., local area network (LAN), hardwire, wireless link,intranet, etc.)

Server systems 10 and client systems 14 may be implemented by anyconventional or other computer systems preferably equipped with adisplay or monitor (not shown), a base (e.g., including at least oneprocessor 15, one or more memories 35 and/or internal or externalnetwork interfaces or communications devices 25 (e.g., modem, networkcards, etc.)), optional input devices (e.g., a keyboard, mouse or otherinput device), and any commercially available and custom software (e.g.,server/communications software, queuing module, dispatching module,browser/interface software, etc.).

Client systems 14 may receive application or other user processingrequests (e.g., remote application processing, database queries, remotedesktop hosting, etc.) for server systems 10. In another example, theprocessing requests may be received by the server, either directly orindirectly. The server systems include a queuing module 16 to generateone or more processing queues and service processes to service theprocessing requests, and a dispatching module 20 to schedule portions ofthe processing requests across the processing queues. Ultimately,modules 16 and 20 allow CPU processing to be allocated among theprocessing requests (e.g., from client systems 14). A database system 18may store information in support of the processing requests (e.g.,databases and indexes, user requests, historical and statistical data,etc.). The database system may be implemented by any conventional orother database or storage unit, may be local to or remote from serversystems 10 and client systems 14, and may communicate via anyappropriate communication medium (e.g., local area network (LAN), widearea network (WAN), Internet, hardwire, wireless link, intranet, etc.).The client systems may present a graphical user interface (e.g., GUI,etc.) or other interface (e.g., command line prompts, menu screens,etc.) to allow users to interact with and utilized the featuresavailable on server systems 10, and to set up CPU provisioningparameters on server system 10 using the techniques described herein.

Alternatively, one or more client systems 14 may perform CPUprovisioning when operating as a stand-alone unit. In a stand-alone modeof operation, the client system stores or has access to the data (e.g.,user requests, historical and statistical data, etc.), and includesqueuing module 16 and dispatching module 20 to perform CPU processmanagement. The graphical user interface (e.g., GUI, etc.) or otherinterface (e.g., command line prompts, menu screens, etc.) allows usersto interact with and utilized the features available on client systems14, and to set up CPU provisioning parameters on client systems 14 usingthe techniques described herein.

Queuing module 16 and dispatching module 20 may include one or moremodules or units to perform the various functions of present inventionembodiments described below. The various modules (e.g., queuing module,dispatching module, etc.) may be implemented by any combination of anyquantity of software and/or hardware modules or units, and may residewithin memory 35 of the server and/or client systems for execution byprocessor 15.

Queuing module 16 and dispatching module 20 implement a granular taskscheduler using a 1:1 threading model rather than an M:N threading modelto allow seamless integration into existing designs that use a kernelthreaded architecture. CPU scheduling is achieved by implementing a runqueue mechanism that allows only a fixed number of kernel threads to bedispatched to the OS CPUs at a time (based on the number of parallelthreads required to fully utilize the system CPUs). Other kernel threadsin the run queues are blocked on wait primitives, creating a similarlevel of control to a solution using an M:N threading model, but withoutthe need to manage a separate set of user and kernel worker threads.When a running thread yields and returns to the run queues, it selectsand unblocks the next thread the scheduler logic indicates is eligibleto run (including continuing to run itself if it's at the head of thequeue).

In order to avoid the need to re-implement the I/O subsystem or OSprimitives, the technique instruments or wraps existing OS calls withcallback hooks that inform the scheduler when a thread is about to blockor unblock when entering or exiting such an operation. Thus, a newthread can be dispatched from the run queues to the CPU when a currentlyrunning thread blocks, or when a thread that is newly eligible to run isadded to the run queues, thereby requesting permission to execute. Withthe thread dispatching mechanism and the 1:1 threading model, threads inthe system can continue to issue I/O calls directly, avoiding anylatencies that might be incurred by handing off such requests toseparate threads as in an M:N threading model. Optimized synchronizationprimitives can also continue to be used as-is without needing to beredesigned with the associated potential performance implications.Similarly, other existing subsystems, such as those that are signalbased, can continue to operate as-is.

Overall this approach prevents the need to re-architect the threadingmodel when adding CPU provisioning capabilities to an existing systemthat uses a 1:1 threading model, greatly reducing the development costsof such an effort. By doing so, the system can retain the key benefitsof a 1:1 threading model including avoiding the need to offload I/Ooperations to a separate subsystem, and or to re-implement highlyoptimized synchronization primitives with an extra layer of logic formanaging control in the user space, thereby ensuring that the workloadmanagement capabilities can be provided with minimal overhead.

In order to provide both an accurate level of CPU control withouttrading off possible scalability, the system uses a hybrid run queuemechanism that combines the scalability aspects of multiple independentrun queues with the scheduling accuracy benefits of using a single runqueue.

In order to avoid potential bottlenecks on system scalability, a set ofindependently serialized run queues are used to dispatch processingrequests, eliminating any global serialization points. The number of runqueues in a typical embodiment would be set to be equivalent to thenumber of CPUs present on the host environment. In some implementations,having a single run queue per processor or processor core can reduce oreliminate latency due to the blocking of one request while anotherrequest is accessing a single queue (i.e., when requests conflict oneprocess has to wait until the single run queue becomes available).Simple load balancing such as a round robin dispatching or scheduling ofincoming threads/tasks, or adding new tasks to the shortest queue can beused to ensure the run queue lengths remain relatively even.

In order to ensure accurate scheduling, scheduling metrics forindividual jobs or workloads, such as share values and recent CPUconsumption, may be stored in a global data area that is shared acrossall run queues rather than per run queue. Such historical data can beused to prioritize scheduling for known processes via the queues tooptimize CPU utilization across available processors to achieve the bestuser and administrator desired outcomes. Contention for access to theshared storage or memory area is limited by implementing these metricsas atomic counters that use simple compare-and-swap instructions ratherthan heavier weight mutexes or latches to ensure minimal potential forbottlenecks. In other words, machine instructions are employed to updateindividual data fields without locking the entire global data set, aswould be the case if a semaphore or mutex were employed. Usage of commonscheduling data implicitly ensures that the prioritization of tasks ineach run queue is based on consistent up to date information, and istherefore implicitly balanced, thereby eliminating both the need foradditional complex load balancing logic and eliminating any accuracytradeoffs from using separately serialized scheduling data that wouldnot be in balance (depending on the distribution of work); leading toless overall accuracy in CPU provisioning.

In order to implement reliable cooperative time slicing or processingresources, while sidestepping roadblocks in typical implementationmentioned above, one embodiment of the present invention introduces theconcept of a lightweight conditional yield check that is based on anoffloaded global clock count. The time slicing mechanism operates byhaving a global timer thread that increments a global clock counter(e.g., as the variable global_clock) on a defined time slice interval.For example, a typical embodiment might select 10 milliseconds (ms) asthe time slice interval, similar to a typical OS time slice. Other timeslice intervals may be employed or varied among queues depending on theruntime environment or based on compiled statistics. For simplicity, theglobal clock may be some multiple of the actual clock (e.g., clock tickmay be accumulated or made less granular such that the global clockincrements once each ms).

A thread running a task on the system caches the current clock value(e.g., as the variable thread_clock) of the global clock count in threadlocal storage. The system or thread is then able to perform checks onwhether the thread's current time slice has expired by performing asimple clock check (e.g., whether the locally cached counter matches thecurrent global clock count or difference in the global clock count). Forexample, a clock check may determine whether the thread_clock variableis greater than or equal to the global_clock variable. Other types ofsimple Boolean tests against the global dock may be used to test threadtimer expiration and are known to those skilled in the art.

By using this technique to perform thread execution timing, it becomesfeasible to place the timing checks at very frequent intervals withinprocessing intensive areas of code without requiring precise timingchecks and without impacting the overall performance of processingoperations. Since the yield check is conditional, it only actuallyyields the current time slice if it has found to have expired, meaningthat reliable and consistent time slice boundaries can now be enforcedso long as the conditional yield checks are hit with at least a minimumfrequency. This completely sidesteps the issues with code paths eitheryielding too frequently and degrading performance, or not yieldingfrequently enough and degrading control.

With the ability to enforce a relatively accurate time slice boundary, arelatively reliable level of control may be maintained over CPUprovisioning without being subject to unbounded variability in timeslice lengths and complexities with how to space out yield points in thecode. This is particularly critical for providing reliable CPU limitcapabilities where the goal is not just to subdivide available CPUcapacity fairly between queued work, but also to ensure that the CPUused by specific workloads does not exceed a certain utilizationthreshold.

In order to track the CPU time used by threads running tasks on thesystem, one embodiment of the present invention leverages both the 1:1threading model and the previously mentioned time slicing mechanism inorder to implement an optimized method for CPU time metric collection.Specifically, the average time slice length is tracked for a particulartask based on a recent moving average for task execution time. If thecurrent time slice is below a target threshold (e.g., 500 microseconds(μs) in a typical embodiment), a scheduling process starts measuring theCPU time on every Nth time slice rather than every time slice in orderto reduce the number of measurements per task, thereby reducing the timechecking overhead relative to productive task execution. This techniqueis feasible due to the fact that a 1:1 threading model is being run, andas such, the same kernel thread continues to execute the same task onsuccessive time slices until completion, allowing additional latitude inchoosing when not to update the CPU time metrics for every time slice.

A challenge when using this type of metric collection mechanism isensuring that if the average time slice length suddenly increases, thesystem can flag it, and not let the task inadvertently consume a largeamount of CPU time before the scheduler can compensate. In order tosolve this potential problem, a rule may be added to the time slicingmodel such that when a time slice ends due to a time slice boundarybeing hit, rather than due to a blocking operation such as an I/O call,the actual CPU consumption time for the slice is measured and the timeslice metrics are updated, regardless of the stored average time slicelength. This technique does not have an appreciable performance impactsince the time slices are relatively long (e.g., a coarse value of 10milliseconds) relative to the metric collection process.

This method of metric collection makes the CPU timing mechanism both lowcost and robust so that various timing models can be implemented. Forexample, a model where the average time slice length is 20 μs, due tofrequent blocking operations, sample times may be every 10 or 20 timeslices so that the time is measured every 200-400 μs, thereby amortizingdown the added overhead. If however, a large 10 ms (10000 μs) time sliceis encountered, a time slice boundary would be crossed, therebyinitiating an immediate CPU query and the scheduler decision is updatedas opposed to continuing to skip CPU measurements only to discover afterthe fact that a task was unintentionally allowed to run for an order ofmagnitude longer than desired.

A basic CPU limit implementation could involve tracking the accumulatedCPU usage for each workload within a particular defined time interval orscheduling cycle, and preventing further dispatches once a workload hasexceeded its relative limit until the beginning of the next schedulingcycle. A scheduling cycle in a typical example embodiment of the presentinvention may be 0.5 or 1 second, i.e., an interval that strikes abalance between queuing and dispatching/scheduling (e.g., by way ofqueuing module 16 and dispatching module 20) ensuring a balance betweenresponsiveness and low CPU overhead. One possible limitation to thisimplementation is that it does not account for tasks currentlydispatched and running when the time limit is hit, and therefore allowsthe current tasks to run until their next time slice boundary.

In order to prevent the potential chronic CPU runtime spillover causedby this effect, one embodiment of the present invention implements CPUlimits by assuming the next time slice executed by a thread is similarto the previously executed time slice, and makes a predictive decisionabout whether that task should be allowed to run during the currentscheduling cycle based on that assumed time slice value. In other words,a determination is made whether or not that thread fits within thecurrent scheduling window. This scheduling technique has the effect ofevening out the likelihood of cases where there is overshoot orundershoot of the target scheduling window.

If a thread is moved or “bumped” to the next scheduling window, theduration of which may be unknown at the time the bump is made, the timeslice boundaries will vary slightly from the target boundary. Tocompensate for such boundary timing errors, the technique implements anerror correction facility that computes the error by comparing theaccumulated CPU usage for a workload at the end of a scheduling cyclewith its target CPU limit. If the CPU limit was encountered, the limitin the next scheduling cycle is adjusted to compensate for any amount ofover or under shooting of the limit in the previous scheduling cycle

The combination of the reliable time slicing and accurate CPU usagemetrics in the embodiments of the present invention described herein, aswell as the usage of predictive dispatching and error correctionmechanisms, ensures that accurate CPU limit enforcement can be achievedwhen operating within the context and limitations of a middlewaresoftware system.

A basic CPU time limit implementation computes CPU time limits byassuming dedicated CPUs and computing a CPU time limit that a workloadmay receive during a particular scheduling cycle as a percentage limitof the total scheduling cycle length multiplied by the number CPU cores(i.e., Δ cycle length×#CPU cores). This calculation is effective innon-virtualized environments, but may not produce correct results whendealing with environments where shared CPU capacity is beingmicro-partitioned and the host is only receiving fractional CPU usage.

In order to support virtualized environments, one example embodimentavails itself of OS specific Application Interfaces (APIs), whenavailable, to determine the total CPU capacity that was available to thevirtual host over the most recent scheduling cycle. The CPU capacityvalue is then used in the CPU limit calculation, as opposed to simplyassuming the available capacity is the scheduling cycle lengthmultiplied by the number CPU cores (i.e., Δ cycle length×#CPU cores).

This ensures that present invention embodiments can provide accuratelimits in virtualized environments as well as non-virtualizedenvironments. In a virtualized environment a hypervisor controls accessto hardware resources. The basic error correction mechanism used forgeneral CPU limits also implicitly helps to compensate from anyinaccuracy resulting from changes in capacity the hypervisor makesbetween scheduling cycles.

Another potential benefit of the embodiments of the present inventiondescribed herein is that a middleware based workload manager canleverage internal state information to avoid priority inversion forsubsystems that may experience high contention between workloads ofdiffering priorities as described above. To further elaborate, a flagmay be passed to the dispatching logic to indicate whether a threadrequesting a time slice is holding a resource being requested by higherpriority threads. In this case the dispatching logic would respond byplacing this time slice request at the front of the run queue so that itwill be given preferential priority to minimize the amount of time thepriority thread waits on the run queue. The bump decision may be madeunder the assumption that the longer the resource holding thread waits,the longer it will hold onto the key resource and potentially impactother higher priority threads that require the same resource. Theflagged resource may be a muter, latch, or any other kind of widelycontended synchronization resource on the system).

The technique further allows tasks that have just obtained a keyresource or synchronization point to jump to the front of the run queueirrespective of their priority, ensuring that a low priority taskholding the resource does not degrade the performance of high priorityprocesses that may be waiting for the resource. Thus, by implementingCPU provisioning in middleware, the queuing and dispatching logic hasinformation about thread resource usage that is not available to OSbased workload managers, thereby enabling re-queuing options that arenot available to such OS based workload managers. Having a workloadmanager within the middleware platform itself also opens up furtherpotential optimizations in other embodiments based on internalinformation such as which tasks are causing the most contention andbetween which internal resources.

A summary of the basic framework of the techniques described aboveprovide the capability for implementing both accurate CPU shares and CPUlimit controls (i.e., CPU provisioning) within a middleware platformwith very low overhead, carrying all the associated benefits of amiddleware integrated solution (consistent platform support, ease ofconfiguration, and the possibility for internal optimization), whileeliminating the majority of the tradeoffs this would imply in terms ofaccuracy, performance overhead, and cost of implementation. Additionaldetails of the various embodiments described above are further describedbelow.

In order to facilitate understanding of the technique described above, aspecific example is now described. By way of example, one embodiment ofthe present invention is described for a workload management dispatcher(WMD) capabilities implemented in DB2® Linux/Unix/Windows (LUW)environment in order to demonstrate how an example embodiment mayoperate in the DB2 environment. First, a threading model is generatedand integrated with OS primitives, i.e., dispatcher control flowoperation as implemented by queuing module 16 and dispatching(scheduling) module 20 (FIG. 1).

For the purpose of description a unit of processing for one or moreprocessing requests to be performed over a single or multiple timeslices by the processing suite is referred to herein as an “agent”(e.g., engine dispatchable units (EDUs) in DB2 parlance). Listing 1below, lists dispatcher logic (e.g., as implemented by dispatchingmodule 20):

When dispatcher logic is active:

-   -   Any agent threads starting to process a request go through the        dispatcher logic to obtain permission to execute.    -   Assuming a dispatch concurrency level of N        -   The first N agent threads are allowed to execute        -   Any subsequent agent threads ready to run, add themselves to            a dispatcher run queue and block to wait for one of the            running threads to complete its current dispatch interval    -   Dispatched or executing agents reach the end of their current        interval (time slice) and dispatch the next waiting agent off of        their run queue when they:        -   Reach the end of their assigned dispatch interval (i.e. by            yielding their current time slice), or        -   Block on a resource (e.g., a lock, I/O wait, etc.)    -   When an agent gave up its interval in order to block or wait,        and is ready to begin executing again, the agent rejoins a run        queue and waits to be dispatched again.

This process is further illustrated in FIG. 2 for a DB2 system. Theability of the WLM dispatcher to control the allocation of CPU betweenactive threads on the system comes from the fact that it restricts, to afixed concurrency level, the number of threads that are allowed to bedispatched and executed in parallel. By doing this the dispatcher isable to control which threads are active against the CPUs (and howoften) when under high CPU load.

A plurality of user processing requests 205 is received for processingby a DB2 system 200. System 200 is implemented by a multiprocessorsystem, and user processing requests 205 are processed by dispatcherlogic 210 (e.g., queuing module 16 and dispatching module 20). The userprocessing requests or agents 205 are divided into requests 205(1) froma first user and 205(2) from a second user; each with different hatchingas viewed in FIG. 2. Queuing module 16 assesses the current processingworkload for the plurality of user processing requests and subdividesthe multiprocessor system into queues and associated servicing threadson a per processing unit basis. Every agent 205 goes through dispatcherlogic 210. Only N agents are dispatched at a given time, while otheragents wait in a queue. The dispatched agents execute according to adefault user service class according to each user request for agents205(1) and 205(2). Service classes are explained hereinafter. Each agentexecutes during its corresponding dispatch interval. At 230, each agent,upon reaching the end of their execution interval, either terminates or“wakens” the next queued agent and re-enters a run queue to awaitdispatch by dispatcher logic 210. This concept is further illustrated inFIGS. 3a and 3 b.

A preferable dispatch concurrency limit, N, is a concurrency level thatprovides enough thread parallelism to enable DB2 to fully utilize theCPUs on system 200. The dispatch concurrency limit ensures that no lossof efficiency occurs when enabling the dispatcher, and therefore no lossin throughput (besides the small path length overhead the dispatcherinfrastructure incurs). It also ensures the dispatcher retains themaximum amount of control possible in terms of its ability to selectwhich threads are dispatched when.

FIG. 3a illustrates a system without a WLM dispatcher. In this example,EDUs 300 are “stuffed” into run queues 310 for processing on processors320, which precludes the middleware server from controlling the amountof CPU resource given to each thread. For example, EDUs in FIG. 3a arequeued without dispatcher logic which leads to an arbitrary division ofCPU between them because no decision is made with respect to thecharacteristics of a particular EDU. In contrast, FIG. 3h illustratesdispatcher run queues 330 for which EDUs 300 correlate, or forsimplicity, may be same as run queues 310. However, in FIG. 3hdispatcher decisions (e.g., via dispatcher logic 210 (FIG. 2)) are madebefore queuing EDUs 300, thereby achieving the desired CPU allocation aswell as additional processing efficiencies described herein.

Allowing a too high concurrency limit, while ensuring full utilizationof the CPUs, reduces the amount of control the dispatcher has over theworkload, as well as adds potential for additional resource contentionbetween running threads. Too restrictive a concurrency level, on theother hand, may cause the CPU capacity on the system to be underutilizedand reduce overall throughput.

A theoretical concurrency limit is the raw number of parallel processorson a system (which corresponds to the number of threads the OS canactually dispatch in parallel), but in practice a concurrency limit maycompensate for latencies incurred between the time a blocked threadposts and the time when the OS actually dispatches the next thread. Inthis example, four processor 320 are shown and enable a concurrencylimit of four (i.e., N=4)

With given dispatch intervals from the dispatcher run queues 330, theWIN dispatcher logic 210 makes scheduling decisions based on externalattributes associated with DB2 service classes. To the WLM Dispatcher,each DB2 service class represents an individual “priority class” fordispatching purposes. By dispatching agents from particular serviceclasses more often than other service classes, the dispatcher is able tocontrol how much CPU time each receives relative to the others, andthereby allocate CPU in such a way as to match the externally configuredsettings.

FIG. 4 illustrates the concept of service classes. The figure shows abasic model of how dispatcher 210 achieves service differentiation interms of the amount of CPU time allocated to agents 205(1) and 205(2)running via two different service classes 400(1) and 400(2). Dispatcher210 tracks the accumulated CPU time consumed by agents executing in eachservice class and resets the aggregate metric at a predetermined timeinterval (e.g., every second). This repeating period is referred to asthe “scheduling cycle,” as mentioned above. Thus, at any given point intime, the service class that is computed as the farthest away from itstarget allocation within the most recent scheduling cycle can beidentified (the calculation performed is based on the accumulated CPUtime consumed in the current scheduling cycle relative to the targetallocation for the service class).

When selecting the next agent to run from its corresponding run queue,the dispatcher logic 210 selects an agent from the service class that isthe furthest away from its target allocation. This ensures theallocation of CPU time between service classes tracks as closely aspossible to the target allocation, irrespective of variations in thelengths of the individual intervals executed and the characteristics ofthe individual workload.

In addition to the basic scheduling mechanism described above, thedispatcher 210 also provides the ability to enforce strict CPUpercentage (%) utilization limits on particular service classes (anexample in the context of the scenario in FIG. 4 would be a 75% CPUlimit on Service Class A 400(1)).

In the scenario illustrated in FIG. 4, the dispatcher continues tooperate in the same manner described above, except that once a serviceclass has exceeded its CPU time limit relative to the current schedulingcycle, the dispatcher does not dispatch any further agents waiting torun from that service class until the next scheduling cycle begins. Thisensures that over time the service class respects the imposed limit.

The dispatcher integrates with low-level “primitive” OS operations viafunctional hooks or dispatcher “callbacks” integrated into the DB2Operating System Services Layer (OSSL). These hooks ensure that anythread under dispatcher control calls back into the dispatcher logic atany time the thread is about to enter or exit a blocking operation. Thiscall back notifies the dispatcher when a thread that is currentlyrunning is about to give up its CPU time slice, as well as when a threadthat was previously blocking requires the CPU again, and further allowsthe dispatcher logic to perform the appropriate scheduling operations toensure the desired concurrency level is maintained for running threadson the system processors.

FIG. 5 illustrates an example dispatcher framework that allows the useof multiple run queues in order to reduce global serialization impactson running work. The framework includes shared scheduling data 500, aplurality of run queues 510(1)-510(N) and scheduler logic 520 (e.g., asimplemented by dispatching module 20). Each run queue 510 is responsiblefor managing a subset of the global dispatch concurrency allowed on thesystem (e.g., as implemented by queuing module 16) with each run queuehaving its own serialization. The threads have associated requests andagents 530. Agents 530 enter one of the run queues to request dispatch,and are either allowed to run (if the concurrency limits for that runqueue have not yet been met), or are forced to queue and wait for adispatch interval to become available if scheduler logic 520 has alreadydistributed all its available dispatch intervals. To enable scalabilityand reduce contention, one run queue object is allocated per physicalCPU core (e.g., as available to DB2 on a given host).

An individual priority class object is allocated within each run queueobject 510 for each service class or workload on a database (allowingthe avoidance of global serialization). Scheduling data 500 for eachqueue 510 is shared across all the run queue objects 510 by default,with the priority class in one of the run queues designated to containthe master scheduling data 500, and all other priority classesreferencing the scheduling data in that priority class. The fields usedin the scheduling data 500 are implemented as atomic counters to allowparallel access for incrementing without requiring full latch or mutexbased serialization.

This model allows a single global view of the resource consumption perservice class to be maintained, which greatly simplifies the process ofload balancing across run queues, while still avoiding the globalserialization associated with queuing using only a single run queue.Because CPU usage and limits for the priority classes are trackedglobally across run queues, this has the effect of automaticallycompensating for any CPU usage skew that would otherwise occur betweentasks dispatched by different run queues. The tracking also ensures thatthe effective priority value for the workload is constant across all therun queues and reflects the most up to date metrics on the system. Whenenforcing CPU limits, the tracking helps ensure that all the availableCPU is consumed on a workload during a particular scheduler cyclewithout needing to look for an individual run queue where that workloadstill has time available. Load balancing logic aids in a reasonabledistribution of queued tasks from a specific workload across run queues,and affects only the contention profile of execution rather than theaccuracy of CPU provisioning.

The time slicing mechanism introduced for the WLM dispatcher 210 may bea frequency based model used to impose a roughly reliable maximumduration for a dispatcher time slice, which helps to ensure that thedispatcher can maintain a minimum degree of dispatching accuracy. Basedon test lab experiments, a target duration of 10 milliseconds isreasonable for a dispatcher time slice. The 10 ms time frame was chosento achieve a reasonable balance between accuracy and overhead, forexample:

-   -   in terms of accuracy, a 10 millisecond interval on 1 processor,        with the default scheduling cycle of 1 second allows control of        CPU utilization at a granularity of 1% increments, which is a        reasonable level granular control that can be externalized to        middleware for CPU limits (e.g., in a DB2 implementation).    -   a 10 millisecond interval is infrequent enough to incur no        measurable performance overhead on the system when enabling the        dispatcher. By way of example, and to put the 10 ins number in        perspective, a representative On-Line Transaction Processing        (OLTP) workload execute on an average time interval in the range        of 50 μs due to frequent client-server communications, and this        incurs a throughput overhead in the range of 2-3% of        transactions completed under test conditions (assuming that no        proactive or beneficial CPU allocation adjustments are made).        The granularity we have chosen here is several orders of        magnitude more coarse than this level.

To implement the above, the concept of a WLM Timer thread is introduced.The WLM Timer thread operates (e.g., at the DB2 instance level), and hasthe purpose of incrementing one or more clock counters as describedabove and in the global control structure on a defined frequency. Thefollowing counter is used and shown in a pseudo “C” programming languageconstruct below:

globalStruct→checkPointTimerCount

The variable checkPointTimerCount is an arbitrary variable that holds aclock count.

Individually executing agents or kernel threads (e.g., EDUs) cache thecurrent values for the counter in their thread local storage. Any timean agent reaches a dispatcher yield checkpoint within the DB2 code, theagents check their local copy of the checkPointTimerCount against theglobal copy in the global control structure to see if there is a match.Accordingly, when the clock count matches or exceeds the requisitecount, the thread will yield execution. Yield checkpoints are placed inany areas of extended processing in the code. These yield checkpointsare generally hit frequently enough that the values typically do matchin the vast majority of cases, in which case no further action isperformed.

If the values do not match however, a time slice boundary is consideredto have been hit, and the thread calls into the dispatcher logic toplace itself back on the run queues to wait for the next available timeslice. By having frequent conditional yield checks instrumented in themiddleware code, this allows instrumentation of relatively reliablegranular time slice boundaries without risking the performance impactsof hitting time slice boundaries too frequently.

A separate kernel thread is used to implement the timer itself to ensurethat the thread would never be able to get blocked on latches or othersynchronization primitives and hence would be able to increment theclock count on (or as close as possible to) the desired boundary.Laboratory experiments indicate that the timer thread can become starvedfor a non-trivial period of time when the system is under very high CPUload (which measurably impacts dispatcher accuracy when enforcing timeslice limits and in extreme cases allowing intervals to run nearly anorder of magnitude longer than they should for CPU bound work). For thisreason, in installations that support it, the thread may be assigned anabsolute or real time priority, ensuring that it can be scheduled firstby the OS when it needs to increment the clock count.

Since CPU time measurement can carry a relatively large overhead,special allowances are made to reduce the overhead for cases where athread is executing very frequently or for short duration time slices. A“time sampling frequency” optimization may be implemented by designatinga value of 20 time slice units in order to indicate that sampling occursonce every 20 time slices. The time sampling frequency is used todetermine:

-   -   how often the CPU time is measured when tinder the threshold        time slice length (T);    -   the period of a moving average (X_(AVG)) updates for recent time        slice CPU times that each thread maintains in order to evaluate        a smoothed average for recent slice execution interval lengths;        and    -   the minimum number of initial time slice samples that are        required before optimization of the time sampling frequency        starts.

A time sampling threshold, T, is defined which represents a thresholdfor time slice length below which optimization within the dispatchersoftware initiates. A heuristically determined threshold value of 500microseconds may be used by default and subsequently updated.

If a thread's average interval length (X_(AVG)) drops below the timesampling threshold, T, measurements of CPU time are taken on the timesampling frequency instead of on each individual time slice. To ensureaccuracy, there is no sampling and estimating—rather multiple timeslices are simply measured at once instead of individual time sliceswhen the average interval length is very short. This reduces the cost ofobtaining CPU time in these cases by an order of magnitude and yields ameasurable improvement in OLTP workloads that use very short time slices(for reference a 1-2% throughput improvement was measured on aninternally maintained performance benchmark).

The optimized sampling mechanism is immediately disengaged if an agententers the dispatcher through a yield checkpoint, thereby ensuring thatthe scheduling mechanism accurately handles cases where an agent threadsuddenly transitions to a CPU intensive code path where it may yield itsdispatch interval infrequently.

This entire optimization is feasible due to the usage of a 1:1 kernelthreading model for the dispatcher which ensures that a particular taskcontinues to execute successive time slices using the same kernelthread, allowing the middleware to bypass measuring the CPU time onevery time slice and still maintain viable metrics for schedulingpurposes.

CPU limits are implemented in the WLM Dispatcher 210 by imposing amaximum limit on the CPU time consumed by a service class over a givenscheduling cycle. In a typical embodiment, a 1 second scheduling cyclecould be used. In many WLM solutions including AIX WLM, Linux WLM, DB2WLM, service classes are subdivided into superclasses and subclasses.The system is divided into superclasses, and each superclass is dividedinto a set of subclasses. The shares and limits employed by thetechniques described herein and configured via the dispatcher may be setat the superclass and subclass layer. When a service subclass orsuperclass has a CPU limit configured, the maximum amount of CPU timethe corresponding dispatcher priority class is allowed to consume in thenext scheduling cycle (m_maxCycleTime) is computed based on the CPUlimit as a percentage of the total CPU time available to DB2 in thescheduling cycle.

A dedicated scheduling thread is responsible for computing the specificCPU limits which are calculated as follows for each individual priorityclass:Max cycle time=% CPU limit×Available cycle timeAvailable cycle time=Scheduling cycle length×# physical cores availableto DB2

During the scheduling cycle, a check is made for the presence of amaximum cycle time limit any time there is an attempt to dispatch a newtask within a particular priority class. Once the cycle time limit hasbeen exceeded, the priority class is removed from the run queues, andany further agent threads waiting to dispatch on that priority class areconfigured to queue and wait. In the case of superclass level limits,all priority subclasses in the relevant priority superclass also areremoved from the run queues.

At the beginning of the next scheduling cycle, the scheduler threadresets the CPU consumption for all priority classes and dispatches anyagent threads queued within priority classes that exceeded their limitsduring the previous scheduling cycle.

One particular technical challenge in the implementation of CPU limitsrelates to the handling of very restrictive limits at high levels ofthread or task concurrency. When the maximum CPU time allowed for agiven priority class in the next scheduling cycle is restrictive enough,and enough agent threads are contending to be dispatched on thatpriority class, it is possible that some subset of these agents each beallowed to execute only a single time slice before the limit for thecycle is exceeded. Because it is not known in advance how much CPU timeeach time slice will consume before it has been executed, and becausemultiple agents can be dispatched in parallel, an estimated time slicelength is relied upon and is based on the previous time slice for whicheach thread executed, in order to decide how many agents to dispatch inan attempt to come as close as possible to the target CPU usage.Inevitably this concept introduces a small but non-trivial degree oferror in any single scheduling cycle since the number of threadsdispatched could be based entirely on predicted data. Without some typeof compensatory mechanism this inaccuracy can build up over timeresulting in missing the mark on imposed time limits (note that this isnot a purely theoretical problem, as this effect was produced duringunit testing during an attempt to enforce a 1% CPU limit underrelatively high utilization and high application concurrency).

One possible approach considered for ameliorating this effect is toincrease the length of the scheduling cycle so as to allow enough timeto smooth out the effects of this type of inaccuracy. Unfortunately thisapproach also yields the undesired side effect of both decreasing thegranularity of scheduling accuracy (with the target allocations beingenforced across a larger timeframe of 5 or 10 seconds rather than everysecond), and also decreasing the responsiveness of the dispatcher toexternal configuration changes.

In order to avoid the above side effects and to keep the dispatchergranularity and/or accuracy in line with similar OS WLM capabilities, anerror correction mechanism for CPU limits is introduced. The errorcorrection mechanism operates by having the scheduler thread maintainhistory of the error incurred in each priority class that exceeded a CPUlimit within recent scheduling cycles.

When the scheduler thread performs processing at the beginning of eachscheduling cycle, the scheduler looks for any priority classes that werepredicted to have hit their CPU limit in the previous cycle, and foreach of these the scheduler computes the difference between their targetmaximum cycle time limit and how much CPU the time intervals completedin that priority class actually consumed (this data is obtained from thediagnostic monitoring metrics collected as part of dispatcheroperation), referred to as the “residual limit error”.

When the scheduler thread computes the priority class cycle time limitfor the next scheduling cycle, it applies the current residual limiterror for that priority class to the limit calculation to compensate forany error incurred in the previous cycle (so for example, if the limitis hit on the previous cycle but actually under consumed the CPU by 150μs, the limit is increased by 150 μs for the next cycle to compensateand smooth out inaccuracies over time). In the rare case where the errorincurred is so large that the error cannot be compensate for during asingle scheduling cycle, compensation is performed to the maximum degreepossible and any remaining residual error is carried forward to beapplied to subsequent cycles.

Unit testing of the error adjustment algorithm has shown that itsignificantly improves our limit accuracy in the aforementioned problemscenario.

In order to support CPU limits correctly in virtualized environments,certain embodiments of the present invention use OS specific APIs (whereavailable) to determine the total CPU capacity that was available to thevirtual host over the most recent scheduling cycle. In such cases theCPU limit calculations described above could be updated as follows:Max cycle time=% CPU limit×Available cycle timeAvailable cycle time=CPU capacity available over previous schedulingcycle

In this case, the CPU capacity would represent the actual CPU cycles ahypervisor had assigned to the current host, allowing the target CPUtime limit to be correctly computed relative to that dynamic capacity.As an example, the AIX operating system makes this information availableto applications through the tot_dispatch_time value returned by thelpar_get_info( ) API call used by AIX.

Priority Inversion Avoidance: priority inversion avoidance is a specificoptimization provided within the DB2 WLM Dispatcher for specific shortduration synchronization primitives that may come under heavy contentionby tasks of differing priorities. The following additions are made inthe dispatcher callback hooks that are invoked when a thread enters orexits a blocking state. If the specific synchronization object isflagged as high priority and the WLM dispatcher requires the thread beblocked on the run queues, the thread is placed at the very front of therun queue so that it is the next thread served. The thread's time sliceis flagged as accelerated. If the specific synchronization object isflagged as high priority, and the last time slice the thread executedwas accelerated, the thread will yield the current time slice tocompensate for any priority boost incurred the last time thesynchronization object (e.g., latch, mutex, critical section) wasobtained or entered.

The priority “boost” when exiting a blocking state ensures that a lowerpriority thread does not impede the progress of high priority threadswaiting on the same synchronization object, as this could otherwise dragdown the performance of the high priority threads such that they are onpar with the lower priority thread. To avoid any scenarios where the lowpriority thread is able to reenter a blocking state on the samesynchronization object within one time slice, thereby allowing it to“cheat” and continually exceed its target CPU allocation, the thread isforced to yield its time slice and re-queue on the run queue beforebeing allowed to compete for the synchronization object if its currenttime slice is flagged as accelerated.

In DB2 LUW, this mechanism is specifically applied to buffer pool pagelatching. When database jobs are reading buffer pool pages for specificobjects, they should briefly latch these in exclusive mode in order tofix them in the buffer pool and ensure they won't be evicted. Ifmultiple jobs are competing for this latch, it can cause higher priorityjobs to slow down as low priority jobs linger in the run queues waitingfor permission to run upon having obtained the latch, where this cancause a high priority workload's CPU allocation to be dragged down tothe same level as a low priority workload's allocation, even for readonly workloads, due to contention on this latch. The priority inversionoptimization above allows this situation to be avoided, which issomething that would not generally be possible in an externallyimplemented OS workload manager.

A manner in which queuing module 16 and dispatching module 20 (e.g., viaa server system 10 and/or client system 14) perform CPU allocationaccording to an embodiment of the present invention is illustrated inFIG. 6. Specifically, a current processing workload for the plurality ofuser processing requests is assessed at step 610. The processingcapability of the multiprocessor system is subdivided into plurality ofprocessing units (e.g. processor or cores) based on the currentprocessing workload at step 620. One or more protected processes (e.g.,kernel threads) are started for each of the user processing requests atstep 630.

A processing queue is generated for each of the processing units at step640. A portion of each user processing request is assigned to one ormore of the processing queues at step 650. The assignment may be basedon a priorities and/or service classes as described herein. The portionof each user processing request is serviced by the one or more protectedprocesses at step 660. The process repeats itself at a periodic timeinterval (e.g., a time slice) at step 670.

It is appreciated that the embodiments described above and illustratedin the drawings represent only a few of the many ways of implementingprocessor provisioning by a middleware software system.

The environment of the present invention embodiments may include anynumber of computer or other processing systems (e.g., client or end-usersystems, server systems, etc.) and databases or other repositoriesarranged in any desired fashion, where the present invention embodimentsmay be applied to any desired type of computing environment (e.g., cloudcomputing, client-server, network computing, mainframe, stand-alonesystems, etc.). The computer or other processing systems employed by thepresent invention embodiments may be implemented by any number of anypersonal or other type of computer or processing system (e.g., desktop,laptop, PDA, mobile devices, etc.), and may include any commerciallyavailable operating system and any combination of commercially availableand custom software (e.g., browser software, communications software,server software, queuing module, dispatching module, etc.). Thesesystems may include any types of monitors and input devices (e.g.,keyboard, mouse, voice recognition, etc.) to enter and/or viewinformation.

It is to be understood that the software (e.g., queuing module,dispatching module, etc.) of the present invention embodiments may beimplemented in any desired computer language and could be developed byone of ordinary skill in the computer arts based on the functionaldescriptions contained in the specification and flow charts illustratedin the drawings. Further, any references herein of software performingvarious functions generally refer to computer systems or processorsperforming those functions under software control. The computer systemsof the present invention embodiments may alternatively be implemented byany type of hardware and/or other processing circuitry.

The various functions of the computer or other processing systems may bedistributed in any manner among any number of software and/or hardwaremodules or units, processing or computer systems and/or circuitry, wherethe computer or processing systems may be disposed locally or remotelyof each other and communicate via any suitable communications medium(e.g., LAN, WAN, Intranet, Internet, hardwire, modem connection,wireless, etc.). For example, the functions of the present inventionembodiments may be distributed in any manner among the variousend-user/client and server systems, and/or any other intermediaryprocessing devices. The software and/or algorithms described above andillustrated in the flow charts may be modified in any manner thataccomplishes the functions described herein. In addition, the functionsin the flow charts or description may be performed in any order thataccomplishes a desired operation.

The software of the present invention embodiments (e.g., queuing module,dispatching module, etc.) may be available on a recordable or computeruseable medium (e.g., magnetic or optical mediums, magneto-opticmediums, floppy diskettes, CD-ROM, DVD, memory devices, etc.) for use onstand-alone systems or systems connected by a network or othercommunications medium.

The communication network may be implemented by any number of any typeof communications network (e.g., LAN, WAN, Internet, Intranet, VPN,etc.). The computer or other processing systems of the present inventionembodiments may include any conventional or other communications devicesto communicate over the network via any conventional or other protocols.The computer or other processing systems may utilize any type ofconnection (e.g., wired, wireless, etc.) for access to the network.Local communication media may be implemented by any suitablecommunication media (e.g., local area network (LAN), hardwire, wirelesslink, intranet, etc.).

The system may employ any number of any conventional or other databases,data stores or storage structures (e.g., files, databases, datastructures, data or other repositories, etc.) to store information(e.g., databases and indexes, user requests, historical and statisticaldata, etc.). The database system may be implemented by any number of anyconventional or other databases, data stores or storage structures(e.g., files, databases, data structures or tables, data or otherrepositories, etc.) to store information (e.g., databases and indexes,user requests, historical and statistical data, etc.). The databasesystem may be included within or coupled to the server and/or clientsystems. The database systems and/or storage structures may be remotefrom or local to the computer or other processing systems, and may storeany desired data (e.g., databases and indexes, user requests, historicaland statistical data, etc.). Further, any data structures may beimplemented by any conventional or other data structures (e.g., files,arrays, lists, stacks, queues, etc) to store information, and may bestored in any desired storage unit (e.g., databases and indexes, a userrequests, historical and statistical data, etc.).

The present invention embodiments may employ any number of any type ofuser interface (e.g., Graphical User Interface (GUI), command-line,prompt, etc.) for obtaining or providing information (e.g., databasesand indexes, user requests, historical and statistical data, etc), wherethe interface may include any information arranged in any fashion. Theinter face may include any number of any types of input or actuationmechanisms (e.g., buttons, icons, fields, boxes, links, etc.) disposedat any locations to enter/display information and initiate desiredactions via any suitable input devices (e.g., mouse, keyboard, etc.).The interface screens may include any suitable actuators (e.g., links,tabs, etc.) to navigate between the screens in any fashion.

The present invention embodiments are not limited to the specific tasksor algorithms described above, but may be utilized for CPU provisioningin any multiprocessor system.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It is further understood that the terms “comprises”,“comprising”, “includes”, “including”, “has”, “have”, “having”, “with”and the like, when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations are apparent to those of ordinary skill in the art withoutdeparting from the scope and spirit of the invention. The embodiment waschosen and described in order to best explain the principles of theinvention and the practical application, and to enable others ofordinary skill in the art to understand the invention for variousembodiments with various modifications as are suited to the particularuse contemplated.

As is appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a system, method or computer programproduct. Accordingly, aspects of the present invention may take the formof an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module” or “system.”Furthermore, aspects of the present invention may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, or device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CD-ROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain, or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, inbaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects of thepresent invention may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Java (Java and all Java-based trademarks and logos aretrademarks of Sun Microsystems, Inc, in the United States, othercountries, or both), Smalltalk, C++ or the like and conventionalprocedural programming languages, such as the programming language orsimilar programming languages. The program code may execute entirety onthe user's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects of the present invention are described with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of theinvention. It is understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions whichimplement the function/act specified in the flowchart and/or blockdiagram block or blocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It should also benoted that each block of the block diagrams and/or flowchartillustration, and combinations of blocks in the block diagrams and/orflowchart illustration, can be implemented by special purposehardware-based systems that perform the specified functions or acts, orcombinations of special purpose hardware and computer instructions.

What is claimed is:
 1. A method implemented by a computer via amiddleware software system for efficiently allocating workload for aplurality of user processing requests among a plurality of processors ina multiprocessor system comprising: assessing a current processingworkload for the plurality of user processing requests; subdividing aprocessing capability of the multiprocessor system into a plurality ofprocessing units based on the current processing workload; starting oneor more processes to service the user processing requests; generating aprocessing queue for each of the processing units; assigning a portionof each user processing request to one or more of the processing queues;servicing the portion of each user processing request by the one or moreprocesses; allocating a variable predetermined time interval to each ofthe processing queues for which portions of the user processing requestsassigned to a corresponding processing queue execute for a correspondingallocated time interval, wherein when a corresponding allocated timeinterval expires, a currently executing user processing request yieldsexecution and signals the next in queue portion of the user processingrequests to begin execution, and when a currently executing userprocessing request finishes execution prior to the expiration of thecorresponding allocated time interval, determining whether to yieldexecution of the corresponding allocated time interval or execute anadditional portion of the user processing requests during thecorresponding allocated time interval.
 2. The method of claim 1, whereinsaid assigning is based on one or more of user processing requestpriority and user processing request service class.
 3. The method ofclaim 2, further comprising collecting metrics associated with each ofthe user processing requests, wherein said processing request priorityis based on the metrics; and allocating a given portion of saidprocessing capability of the multiprocessor system to a given userprocessing request service class when a user processing request serviceclass is employed.
 4. The method of claim 1, wherein a number of saidplurality of processing units determines an associated concurrency levelnumber for the multiprocessor system for which a corresponding number ofprocessing queues are generated and said servicing includes concurrentlyservicing portions of the user processing requests at the front of eachcorresponding processing queue; and wherein when one of the portions ofthe user processing requests is executing any remaining portions of theuser processing requests are blocked from execution and when said one ofthe portions of the user processing requests finishes executing or whena processing time allocated to a given processing queue associated withsaid one of the portions of the user processing requests expires a nextscheduled portion of the user processing requests are unblocked fromexecution.
 5. The method of claim 1, further comprising collectingmetrics associated with each of the user processing requests andcomputing a moving average of the actual execution time associated witheach variable predetermined time interval, and when the variablepredetermined time interval drops below a threshold, reducing thesampling rate for collecting said metrics to an interval that is amultiple of a corresponding actual execution time.
 6. The method ofclaim 1, further comprising determining when a portion of a userprocessing request is holding a resource needed by a higher priorityuser processing request; and re-queuing the portion of the userprocessing request holding the resource to the front of one of theprocessing queues.
 7. The method of claim 1, further comprising:allocating a shared memory area to be shared by each of the processingqueues; dedicating a portion of the shared memory area to each of theprocessing queues; and maintaining a counter by each of the processingqueues in order for each of the processing queues to time execution ofsaid user processing requests or portions thereof.